The present invention relates to asynchronous digital circuit design and in particular to an asynchronous static random access memory.
The ever increasing demand for simultaneously faster and more complex digital circuits, e.g., microprocessors, has pushed conventional digital circuit design methodologies to their limits. Because of the combination of high clock rates (i.e., greater than 100 MHz) and design complexity (e.g., very large scale integration (VLSI) devices with 10 million or more transistors), signal propagation delay has become a dominant design consideration. It has become clear that a significant design paradigm shift will be necessary if digital circuit design is to continue its historical adherence to Moore's law.
Asynchronous VLSI is an active area of research and development in digital circuit design. It refers to all forms of digital circuit design in which there is no global clock synchronization signal. Delay-insensitive asynchronous designs, by their very nature are insensitive to the signal propagation delays which have become the single greatest obstacle to the advancement of traditional design paradigms. That is, delay-insensitive circuit design maintains the property that any transition in the digital circuit could have an unbounded delay and the circuit will still behave correctly. The circuits enforce sequencing but not absolute timing. This design style avoids design and verification difficulties that arise from timing assumptions, glitches, or race conditions.
Generally speaking, synchronous design styles are facing serious performance limitations. Certain asynchronous design methodologies also have difficulties with some of the same types of limitations, e.g., race conditions. By contrast, the delay-insensitive branch of asynchronous digital design, because of its relative immunity to these limitations, appears to hold great promise for supporting future advancements in the performance of digital circuits.
For background information regarding delay-insensitive asynchronous digital design, please refer to the following papers: A. J. Martin, “Compiling Communicating Processes into Delay-Insensitive Circuits,” Distributed Computing, Vol. 1, No. 4, pp. 226–234, 1986; U. V. Cummings, A. M. Lines, A. J. Martin, “An Asynchronous Pipelined Lattice Structure Filter.” Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, 1994; A. J. Martin, A. M. Lines, et al, “The Design of an Asynchronous MIPS R3000 Microprocessor.” Proceedings of the 17th Conference on Advanced Research in VLSI, IEEE Computer Society Press, 1997; and A. M. Lines, “Pipelined Asynchronous Circuits.” Caltech Computer Science Technical Report CS-TR-95-21, Caltech, 1995; the entire disclosure of each of which is incorporated herein by reference for all purposes.
See also U.S. Pat. No. 5,752,070 for “Asynchronous Processsors” issued May 12, 1998, and U.S. Pat. No. 6,038,656 for “Pipelined Completion for Asynchronous Communication” issued on Mar. 14, 2000, the entire disclosure of each of which is incorporated herein by reference for all purposes.
If asynchronous digital design techniques are to be the digital design methodology which enables the performance of digital circuits and systems to continue to improve in accordance with historical norms, the basic building blocks of such circuits and systems must be provided which rival and exceed the performance of their synchronous counterparts. An example of such a basic building block is the static random access memory (SRAM).
The conventional synchronous circuitry from which such SRAMs are typically constructed is well known. However, as the size of SRAM state elements has decreased, conventional SRAM designs have become more challenging with respect to the increased sensitivity to variations in delay. On the other hand, the insensitivity to delay characterizing some asynchronous design styles presents an opportunity to address such issues.
It is therefore desirable to provide an asynchronous environment in which conventional SRAM state elements may be successfully employed.